1. Technical Field
The present invention relates to semiconductor devices and processes, and more particularly to strained semiconductor materials suitable for different polarity devices on a same substrate.
2. Description of the Related Art
Strained silicon is being used by the semiconductor industry to improve transistor performance. Increased strain levels are desired in future technology nodes (e.g., 32 nm and beyond) to continue to improve transistor performance. In general, there are two methods to apply strain on devices: global and local strain engineering. Global biaxial tensile strain can be readily achieved by growing Si on relaxed SiGe buffer layers, which are grown epitaxially on a Si wafer. However, biaxial tensile strain offers a small enhancement in transistor performance (See, e.g., K. Rim. et al., “Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs,” Symp. VLSI Technol., pp. 98-99, 2002.).
Local strain engineering is the standard method to exert uniaxial tensile and compressive strain on n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs), respectively (see, e.g., X. Chen et al., U.S. Pat. No. 7,361,539). Uniaxial tensile strain can be obtained, for example, by depositing a nitride layer on the transistor (as described e.g. in U.S. Pat. No. 7,361,539) or by forming embedded SiC source/drain structures (See, e.g., Z. Ren, et al., “On implementation of embedded phosphorus-doped SiC stressors in SOI nMOSFETs”, Symp. VLSi Tech., pp. 172-173, 2008). Uniaxial compressive strain is achieved by either depositing nitride layers (e.g., U.S. Pat. No. 7,361,539) or by embedded SiGe (see e.g. T. Ghani et al., “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors”, IEDM Tech. Dig., p 11.6.1, 2003). Both methods loose their effectiveness as the technology is scaled and the transistor pitch becomes smaller (Z. Luo et al., “High performance transistors featured in aggressively scaled 45nm bulk CMOS technology”, Symp VLSI Tech., pp. 16-17, 2007).
Furthermore, a dual stress liner (DSL) method, where nitride layers with opposite strains are deposited on n- and p-channel transistors leads to significant process complication and faces great challenges in future technology nodes. To increase the transistor performance in the future technology nodes, the amount of strain transferred to the transistors needs to be increased.
One way to increase the strain is to combine the global biaxial tensile strain, for example, in a strained silicon directly on insulator (SSDOI) structure, with local strain engineering. While biaxial tensile strain has a small beneficial effect on NFET performance, it deteriorates PFET device performance. Hence, there are several proposals to relax the biaxial tensile strain on PFETs by optimizing the layout or by amorphizing the source/drain regions of the PFETs via proper ion implantation and subsequent annealing.
To benefit even more from global strain engineering, it is desired that the biaxial strain is converted to uniaxial strain by preferential relaxation of the strain. Electron mobility enhancement up to 100% is achieved if biaxial tensile strain in SSDOI is converted into uniaxial strain by proper layout design. The methods proposed by T. Irisawa, et al., “Electron Transport Properties of Ultrathin-body and Tri-gate SOI nMOSFETs with Biaxial and Uniaxial Strain”, IEDM Tech. Dig., 2006), and P. Hashemi et al., “Electron Transport in Gate-All-Around Uniaxial Tensile Strained-Si Nanowire n-MOSFETs”IEDM 2008 use large anchor structures at the end of an active region (in a dog-bone structure) to hold the strain during device processing. Such structures impose severe area penalties and manufacturing cost.
The prior art does not provide a manufacturable solution to integrate NFET and PFET devices on a same chip. While transferring the global biaxial tensile strain into uniaxial tensile strain is advantageous for NFETs, it deteriorates PFET performance, among other things.